The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
A particular challenge, and one which has become increasingly difficult for reduced device geometries, relates to the substrate planarization requirements during device fabrication. To meet such requirements, chemical mechanical polishing (CMP) is a process that has been introduced and used throughout the semiconductor industry, and which continues to be developed. In a conventional CMP process, a substrate surface is acted upon by a slurry and a polishing pad. By way of example, a force may be applied to press the substrate against the pad while the substrate and the pad are rotated. The rotation and the substrate-to-pad force, in conjunction with the slurry supplied to the substrate, serve to remove substrate material and thus planarize a surface of the substrate. In general, a CMP process should be optimized for specific process conditions such as the material being polished, device structure, desired etch rate, etc. With the continued advancement of highly-scaled IC technology, bringing with it new materials and new device structures, optimization of CMP processes not proved entirely satisfactory in all respects.